# 获取当前Tcl脚本所在的目录
set script_dir [file dirname [info script]]

# 定义相对路径文件名
set filename "../sources_1/new/compile_time.v"

# 构建完整文件路径
set full_path [file normalize [file join $script_dir $filename]]

# 获取当前时间，格式化为 "YYYY-MM-DD HH:MM:SS"
set current_time [clock format [clock seconds] -format "%Y-%m-%d %H:%M:%S"]

# 定义完整的 Verilog 模块内容
set verilog_content "reg  [159:0]    compile_time_buff    =   \"$current_time \";\n\n"

# 写入文件内容（覆盖模式）
if {[catch {open $full_path w} file_handle]} {
    puts "Error: Could not open file '$full_path' for writing: $file_handle"
    # exit 1
}
puts $file_handle $verilog_content
close $file_handle

puts "Successfully wrote '$full_path' with current build time: $current_time"

# exit 0